1. Field of the Invention
The present invention relates to semiconductor memory devices and making methods thereof and it particularly relates to a semiconductor memory device having a nonvolatile memory structure and a making method thereof.
2. Description of the Related Art
It is a nonvolatile memory that is one of integrated semiconductor memories assembled in a large scale integrated (LSI) device or chip. This is a device that retains memory information even after a power supply for an LSI chip is turned off and this is an extremely important device to use the LSI chip for various applications.
For the nonvolatile semiconductor device, the so-called float gate type memory or a memory using an insulative film is described in Physics of Semiconductor Devices, 2nd edition, pp 496 to 506 written by S. Sze, A. Wiley-Interscience Publication. According to the description, those memories using the insulative film, in which insulative films are laminated and charges are stored at the boundary thereof or traps in the insulative films, require no additional formation of a conductive film compared with the float gate type. Accordingly, it has been known that the memories can be formed with good matching to the CMOS LSI process.
However, since existent memories storing charges in the insulative films are required to conduct charge and discharge of electric charges while possessing sufficient charge retaining characteristics, they are difficult to realize. On the other hand, it has been proposed to rewrite the memory information by injecting charges of different polarity. The operation is described in Symposium VLSI Technology, p63, 1997. In this structure, a polycrystal silicon gate for memory operation and a gate for cell selection are formed separately. Further, similar descriptions are also found in U.S. Pat. No. 5,969,383.
It is considered that the memory cell structure is fundamentally based on the N-channel metal-oxide semiconductor (NMOS) two transistors in which comprising a memory gate 501 is disposed on the side of a selection gate 502 as shown in FIG. 1.
Diffusion layer electrodes 202 and 201 are disposed to face each other in a silicon substrate 101, and the selection gate 502 and the memory gate 501 are disposed between the electrodes 202, 201 by way of insulative films 902 and 901. Channels 302 and 301 are formed in the semiconductor substrate in association with the gates respectively. FIG. 2 shows the structure as an equivalent circuit. The gate insulative film 901 of the memory gate is formed as a structure of sandwiching a silicon nitride film between silicon oxide films, that is, the so-called MONOS structure (Metal Oxide Nitride Oxide Semiconductor (Silicon)). The gate insulative film 902 for the selection gate 502 is a silicon oxide film. The diffusion layer electrodes 202 and 201 are formed by using the selection gate and the memory gate as a mask respectively. In this case, the selection gate means a gate corresponding to the selection transistor 1 and the memory gate means a gate corresponding to the memory transistor 2 in the equivalent circuit.
It is considered that the basic operations of the memory cell include four stages of (1) writing, (2) erasing, (3) retaining, and (4) reading. However, nomination for the four states is used for typical operation, and writing and erasing may be called in the opposite manner depending on the view. Further, while the operations are explained also with respect to typical ones, various different operation methods may be conceivable. While a memory formed with the NMOS type is to be described for the sake of explanation, this can be formed in principle with the PMOS type in the same manner.
(1) Upon writing, a positive potential is applied to the diffusion layer electrode 201 on the side of the memory gate, and a ground potential identical with that for the substrate 101 is applied to the diffusion layer electrode 202 on the side of the selection gate. A gate overdrive voltage higher than that of the diffusion layer electrode 201 on the side of the memory gate is applied to the memory gate 501, to thereby turn on the channel 301 below the memory gate 501. In this case, the on-state is attained by setting the potential for the selection gate to a value higher by 0.1 to 0.2 V than the threshold value for the potential of the selection gate. At this time; since a most intense electric field is generated near the boundary between the two gates 901 and 902, many hot electrons are generated in this region and injected to the memory gate. This phenomenon has been known as a source side injection (SSI). The phenomenon is reported by A. T. Wu, et al. in IEEE International Electron Device Meeting, Technical Digest, in pp 584 to 587, 1986. While the float gate type memory is used, the injection mechanism is the same also in the insulative film type. The hot electron injection in this system is characterized in that since the electric field is concentrated near the boundary between selection gate and the memory gate, electrons are injected concentrically to the end of the memory gate on the side of the selection gate. Further, while the charge retention layer is formed of the electrode in the float gate type, since electrons are accumulated in the insulative film in the insulative film type, electrons are retained in an extremely narrow region.
(2) Upon erasing, a negative potential is applied to the memory gate and a positive potential is applied to the diffusion layer 201 on the side of the memory gate. This causes strong inversion in a region where the memory gate 901 and the diffusion layer 201 overlap with each other at the end of the diffusion layer. The strong inversion causes a band-to-band tunnel phenomenon and holes can be generated. The band-to-band tunnel phenomenon is reported, for example, by T. Y. Chan, et al. in IEEE International Electron Device Meeting, Technical Digest, pp 718 to 721, 1987. In the memory cell, the generated holes are accelerated in the direction of the channel, attracted by the bias of the memory gate and injected into the MONOS film to conduct the erasing operation. That is, the threshold value of the memory gate increased by the charges of the electrons can be lowered by the charges of the injected holes. This erasing system is characterized in that since the holes are generated at the end of the diffusion layer, holes are injected concentrically to the end of the memory gate 501 on the side of the diffusion layer.
(3) Upon retention, the charges are retained as the charges of the carriers injected into the insulative film MONOS. Since transfer of the carriers in the insulative film is extremely small and slow, charges can be retained favorably even when the voltage is not applied to the electrode.
(4) Upon reading, a positive potential is applied to the diffusion layer on the side of the selection gate and a positive potential is applied to the selection gate 502, to thereby turn on the channel 302 below the selection gate. Then, by applying an appropriate memory gate potential capable of distinguishing the difference of threshold values of the memory gate which are applied depending on writing and erasing states (that is, an intermediate potential for the threshold value between the writing state and the threshold value in the erasing state), retained charge information can be read out as a current.
FIG. 3 shows a cross-sectional structure of a memory cell for providing the prior art described above. FIG. 3 shows an example of the so-called split gate type cell structure. Such an example is shown, for example, in JP-A No. 2002-231829. To improve the scalability of a memory cell using the split gate type cell structure, memory gate fabrication by the so-called sidewall spacer using polycrystal silicon of high fabricability is useful. FIG. 3 shows a typical example. Diffusion layer electrodes 201 and 202 are formed to face each other in a semiconductor substrate 101. A selection gate 502 and a memory gate 501 are disposed corresponding to respective channels 205 and 206 formed between the diffusion layer electrodes 201 and 202. The selection gate 502 and the memory gate 501 are formed by way of gate insulative films 902 and 901, respectively. In this example, silicide layers 554, 555 are disposed over the diffusion layer electrodes 201 and 202 and the gates 501 and 502, respectively.
The structure is advantageous in that injection of holes can be facilitated by decreasing the gate length (Lmg) of the memory gate. However, when the structure is formed by utilizing a usual sidewall spacer, while the gate length can be reduced, this poses a problem in that the wiring resistance of the memory gate electrode is increased. The problem of the wiring resistance is unfavorable for integrated semiconductor nonvolatile memory cells. This is because the conductor layer for the gate has to be handled as wiring when the memory cells are arranged in an array. For example, increase of the gate resistance makes the bias supply instable, which gives a significant problem to the high-speed operation of the cell. In view of the above, to solve the problem, it may be conceivable to silicide the gate electrode formed of polycrystal silicon which has been used frequently in the existent CMOS in order to decrease the gate resistance.
FIG. 3 shows the state where an existent salicide process is applied. Silicide layers 554 and 555 are formed over the gates 501 and 502, respectively. As can be seen from the figure, the memory gate where the gate length (Lmg) is shorter than the gate length (Lcg) of the selection gate involves a problem in that the resistance can not be lowered sufficiently due to the size dependence of the silicide material. The countermeasure for the problem results in an additional problem. That is, when the silicide layer is formed to be large in thickness (xm) in order to lower the resistance of the gate conductor layer, the thicknesses of the silicide layers 254 and 255 for the respective diffusion layers 202 and 201 which have to be formed by the same step also increases. Accordingly, it is necessary to make the diffusion layers 201 and 202 further deeper. This deteriorates the scalability of the cell.
Further, in this example, since the memory gate is formed as a sidewall spacer by polycrystal silicon, when the diffusion layer electrodes 201 and 202 on the side of the semiconductor substrate and the upper portions of the gates 502 and 501 are silicided simultaneously, it may be probably that the diffusion layers, that is, the silicide 555 and the silicide 554 are short circuited to each other. To avoid the problem, a process of forming the material layer for silicidation so as to cover only the diffusion layers on the side of the semiconductor substrate has been described in JP-A No. 2002-231829. However, the method additionally poses a problem in that the resistance of both the selection gate and the diffusion layer cannot be lowered simultaneously.
On the other hand, to lower the resistance without using the siliciding reaction, it may be conceivable to form a memory gate by using a high melting metal such as tungsten. However, this not only makes the fabricability difficult compared with the case of using polycrystal silicon but also makes it impossible to form the source and drain diffusion layer electrodes by a self-alignment process by ion implantation using the gate as a mask. This is because the metal is injected from the gate used as a mask into the substrate due to the knock-on phenomenon caused by ion implantation.